Until now, the signal voltage swing and signal margin of emitter coupled logic, ECL, has been controlled by a single on-chip voltage reference circuit. The disadvantage of this conventional approach is that voltages are only accurately referenced to power supply levels physically near the reference circuits. The voltage drops associated with power supply currents cause the actual power supply levels to vary considerably across the semiconductor chip and invalidate the reference voltages. This has been found to be particularly true when ECL logic is used in the design of VLSI BiCMOS circuits.
FIG. 1 illustrates a standard ECL gate. It comprises differential pair 2 (which includes N-type bipolar transistors 01 and 02) and source follower stage 4. N-type bipolar transistors 04 and 05 are connected together so as to form the output of the gate. The gate's power dissipation is controlled by the VREF1 signal (VREF1 being a voltage). If transistor 03 is kept out of saturation during its operation, then current Ics (through resistor R connected to the emitter of transistor 03) is equal to (VREF1-VBE)/R. The VREF1 voltage controls the output voltage swing of the gate. It can be seen that the difference between the high and the low output levels of this gate is Ics*R and that this is a voltage drop across the pull-up resistor of the differential pair. The input trip point of this gate is set up by a VREF2 signal voltage between power supply voltage VCC and the voltage at the base of transistor 02. If the input of this ECL gate (node IN) is driven by the signal from the output of another ECL gate similar to this gate, then VREF2 has to be set at the midpoint of this output voltage swing to achieve maximum signal margin and performance. If VREF1 and VREF2 are kept at constant levels, then voltage drops on the VCC and VEE power lines will invalidate both voltage references.
FIGS. 2A and B illustrate the physical layout of VCC and VEE power supply pads on a chip and an associated graph. In this figure, the pads are near each other. The band-gap reference circuit which produces voltages VREF1 and VREF2 is placed near the power pads and blocks of ECL circuits are placed at increasing distances away from the power pads. Resistances in the power lines are shown modeled as resistors R.
The graph in FIG. 2B illustrates selected voltages vs. distance. The X axis gives the distance from the power pads of the corresponding ECL circuit shown above it and the Y axis shows the voltage of major signals in the ECL gates. The voltage drops along the VCC and VEE power lines are shown here in the graph as the dark regions. The ECL circuit at the end of the power lines suffers the most voltage drop. Because VREF1 and VREF2 are referenced to the power pads, they are at a constant level regardless of how far they are away from the pads. However, the current reproduced by VREF1 at the local ECL circuit is not constant. This will effect the low output voltage of ECL gates along the power lines. The high output of the ECL gate is also lowered by voltage drops in the VCC line. These effects severely degrade the signal margin. If the voltage drops in the power line are greater than one half of output voltage swing, this will probably result in complete chip operation failure.
FIGS. 3A and B illustrate an example of a SRAM which is designed to fit in a standard JDEC package. FIG. 3B also illustrates a corresponding graph of selected voltages vs. distance, a similar type of plot to that illustrated in FIG. 2B. It has the power pads at opposite ends of the chip. The effects of the power line voltage drops are almost the same except that now the signal voltage swings are larger and may cause catastrophic failure due to the forward biasing of the next ECL stages which are receiving output signals.
FIGS. 4A and B illustrate multiple (two) band-gap reference circuits in a configuration similar to that shown in FIGS. 2 and 3A. FIG. 4B additionally illustrates a corresponding graph of selected voltages vs. distance. Two band-gap circuits are placed at each end of the package. Large layout areas are required for this scheme. Additionally, the critical location of these reference circuits reduce the effectiveness of the scheme. The ECL circuits farthest from the reference circuits still suffer signal degredations and still depend on how much power line voltages have dropped at their location. A similar problem arises in other circuits involving current mode logic, CML, gates. FIG. 5 illustrates a standard CML gate comprising differential pair 2 comprising transistors 01 and 02 connected to transistor 03. It can be easily seen that variations in either the value of VREF1 or VEE will cause variations in the signal swing as well as the current drawn by this gate. Furthermore, variations in VREF2 or VCC can adversely impact the noise margin required to make this circuit element function reliably. The effect of the reference voltage on current of a BiCMOS/ECL circuit block is shown in FIG. 6, which illustrates the variation in current IEE with respect to reference voltage variation.